1. Field of the Invention
The present invention relates generally to a method for forming an interlevel dielectric (ILD) layer, and more specifically to a method for forming an etch resistance interlevel dielectric (ILD) layer.
2. Description of the Prior Art
Multilevel metallization processes have been hitherto greatly applied on very large scale integration (VLSI). Before the metallization of a wafer, an interlevel dielectric (ILD) layer has to be deposited on the wafer in order to insulate the MOS transistor on the wafer from the connecting wires made in later processes to prevent the occurrence of short circuits. With the shrinking of the connecting wires in the wafer production, the properties and the quality of the ILD layer between each connecting layers are of great concerns.
Therefore, it becomes an important issue about depositing an uniform interlevel dielectric (ILD) layer without voids on a surface of a wafer, for enhancing the electrical performances of semiconductor components, such as the reliability.